CIS 451: Computer Architecture (Winter 2013)

Instructor: Andrew Kalafut
Email: kalafuta at gvsu dot edu
Office: C-2-210 MAK
Office hours: MWF 10:00 - 11:00 AM, 1:00 PM - 2:00 PM
Lab Office hours: Th 2:00 PM - 3:00 PM (A-1-167 MAK)

Please read the syllabus
Required text: Digital Design and Computer Architecture, 2nd Edition, by Harris and Harris

This web site should be considered an official form of communication for this class and should be checked often. I will try to make the schedules posted below as accurate as possible, but they are subject to change.

Additionally, please keep up with your grades on blackboard. Also, please make use of the message board set up on piazza.com.


Exams

Midterm Exams

The Midterm Exams are tenatively scheduled for February 11, 2013 and March 25, 2013. Please read the study guide for exam 1 and the study guide for exam 2.

Final Exam

The Final Exam is scheduled for April 24, 2013 10:00 - 11:50 AM. Please read the study guide

Presentations

Presentations will be held the last week of class. These are worth 5% of your grade. Please see the assignment description for details.

Lab Schedule

Date AssignedTopicAssignmentDue Date
1/10/2013 Breadboards Lab 1 - Digital Logic Lab 1/17/2013
1/17/2013 JLS into Project 1 - JLS ALU 2/6/2013
1/24/2013 Sequential Circuits Lab 2 - Sequential Circuits 1/31/2013
1/31/2013 Instruction Sets Lab 3 - Instruction Types 2/7/2013
2/7/2013 Single Cycle CPU Project 2 - Single Cycle CPU 2/27/2013
2/14/2013 Microinstructions Lab 4 - Microcoding lab 2/21/2013
2/21/2013 Pipelining Lab 5 - Pipelining lab 2/28/2013
2/28/2013 More pipelining Lab 6 - Pipeling optimization lab 3/14/2013
3/7/2013 No lab - Spring break None N/A
3/14/2013 Control Unit Project 3 - Single Cycle CPU control 4/3/2013 4/10/2013
3/21/2013 x86 architecture Lab 7 - x86 machine language 3/28/2013
3/28/2013 Machine differences Lab 8 - Machine differences 4/4/2013 4/11/2013
4/4/2014 Cache Lab 9 - Cache 4/11/2013 4/18/2013
4/11/2013 I/O Lab 10 - I/O Finish presentation work and lab 9 4/18/2013
4/18/2013 Presentations None N/A

Lecture Schedule

DateTopicReading
M 1/7/2013 Course introduction Chapter 1
W 1/9/2013 Two level logic Chapter 2.1 - 2.4
F 1/11/2013 Multilevel logic 2.5 - 2.7
M 1/14/2013 Combinational logic design 2.8 - 2.10
W 1/16/2013 Arithmetic circuits 5.1 - 5.2, 5.6 - 5.7
F 1/18/2013 Sequential logic 3.1 - 3.2.2
M 1/21/2013 No Class - MLK Day none
W 1/23/2013 Flip flops 3.2.3 - 3.2.8
F 1/25/2013 Synchronous logic 3.3 - 3.7
M 1/28/2013 Assembly language 6.0 - 6.2
W 1/30/2013 Instruction types 6.3
F 2/1/2013 Addressing 6.5
M 2/4/2013 Single Cycle CPU 7.3
W 2/6/2013 More single cycle CPU None
F 2/8/2013 Review for Exam 1 None
M 2/11/2013 Exam 1 Study!
W 2/13/2013 Microcode TBA
F 2/15/2013 Pipelining 3.6, 7.5.0
M 2/18/2013 Exam 1 discussion None
W 2/20/2013 Data hazards 7.5.1 - 7.5.3
F 2/22/2013 Control hazards 7.5.3
M 2/25/2013 Pipelined processor performance 7.5.5
W 2/27/2013 Compiler optimizations None
F 3/1/2013 Exceptions 7.7
M 3/4/2013 No Class - Spring Break none
W 3/6/2013 No Class - Spring Break none
F 3/8/2013 No Class - Spring Break none
M 3/11/2013 Branch prediction 7.8.2
W 3/13/2013 Superscalar processors 7.8.2 - 7.8.5
F 3/15/2013 Multiprocessors 7.8.6 - 7.8.9
M 3/18/2013 x86 architecture 6.8
W 3/20/2013 x86 microarchitecture 7.9
F 3/22/2013 Review for exam 2 None
M 3/25/2013 Exam 2 Study!
W 3/27/2013 Memory implementation 5.5
F 3/29/2013 Memory systems 8.1 - 8.2
M 4/1/2013 Cache structure 8.3
W 4/3/2013 Cache structure None
F 4/5/2013 Exam 2 discussion None
M 4/8/2013 Memory mapped and programmed I/O 8.5, 8.8.3
W 4/10/2013 PC I/O Systems 8.7
F 4/12/2013 Storage systems None
M 4/15/2013 Review for final None
W 4/17/2013 Presentations Attend and pay attention
F 4/19/2013 Presentations Attend and pay attention
W 4/24/2013 Final exam (10:00 - 11:50) Study!